The availability of detailed reference designs, combined with the chip’s QFN-68 package (which is relatively straightforward to hand-solder with proper equipment), has made the RTL9210B a favorite among hardware hobbyists and open-source hardware communities.
USB differential traces must maintain a strict 90-ohm differential impedance. PCIe traces require 85-ohm differential impedance, while SATA traces require 100-ohm differential impedance. Capacitor Placement: Decoupling capacitors ( ) must be positioned as close as possible to the VDD10cap V sub cap D cap D 10 end-sub VDD33cap V sub cap D cap D 33 end-sub pins to filter out high-frequency switching noise.
The RTL9210B achieved near line rate for USB 3.1 Gen 2 (~10 Gbps raw → ~1050 MB/s usable after overhead).
The remains a vital document for anyone designing or repairing NVMe-to-USB adapters. It captures a mature phase of the chip’s development—after the early bugs were documented but before the shift to USB4 in late 2022.
Supports BOT (Bulk-Only Transfer) and UASP (USB Attached SCSI Protocol) for optimized data transfer 1.2.1. M.2 SSD Compatibility rtl9210b datasheet 2021
While the datasheet only provides theoretical maximums, third-party 2021 tests (using CrystalDiskMark on USB 3.1 Gen 2 host) consistently showed:
Supports USB 3.2 Gen 2 (SuperSpeed Plus) up to 10Gbps 1.2.1.
interface that allows the controller to automatically detect and switch between USB-to-PCIe and USB-to-SATA modes depending on the installed drive. Power Management
Supports PCIe Gen3 x2 lanes, delivering up to 16 Gbps of theoretical bandwidth to the NVMe drive. This ensures the 10 Gbps USB bus remains the only bottleneck. Capacitor Placement: Decoupling capacitors ( ) must be
Modifies activity LED behavior, idle states, or color-coded indicators.
This article compiles and explains the key sections from the official 2021 documentation, which was released to address issues found in earlier 2019-2020 silicon (e.g., overheating and UASP negotiation failures).
Thanks to its versatility and features, the RTL9210B is the chip of choice for many products, including:
As of early 2021, firmware updates improved compatibility for varied SSD models. Update Tools : Most updates use the UTHSB_MPtool on Windows. Unbricking It captures a mature phase of the chip’s
A dedicated GPIO pin can be mapped via firmware to act as a physical hardware write-protect switch. When pulled low or high (depending on configuration), the controller intercepts incoming USB SCSI write commands and returns a "Write Protected" status code to the host OS, protecting data from malware or accidental erasure. Safe Disconnection Mechanism
The 2021 datasheet provides updated power figures measured at 25°C ambient, with a Samsung PM981a 1TB NVMe SSD:
USB Mass Storage Class Bulk-Only Transport (BOT) and USB Attached SCSI Protocol (UASP). UASP enables parallel command queuing, which drastically improves random read/write IOPS. Storage Interfaces
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